ARM Cortex-X4

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The ARM Cortex-X4 is a high-performance CPU core from Arm, released in 2023 as part of Arm's "total compute solution."[1] It serves as the successor of ARM Cortex-X3. X-series CPU cores generally focus on high performance, and can be grouped with other ARM cores, such as ARM Cortex-A720 or/and ARM Cortex-A520 in a System-on-Chip (SoC).[2][3][4][5]

ARM Cortex-X4
General information
Launched2023
Designed byARM Ltd.
Performance
Address width40-bit
Cache
L1 cache128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core
L2 cache512–2048 KiB per core
L3 cache512 KiB – 32 MiB (optional)
Architecture and classification
MicroarchitectureARM Cortex-X4
Instruction setARMv9.2-A
Physical specifications
Cores
  • 1–10 per cluster
Products, models, variants
Product code name(s)
  • "Hunter ELP"
Variant(s)
History
Predecessor(s)ARM Cortex-X3
Successor(s)ARM Cortex-X5

Architecture changes in comparison with ARM Cortex-X3[edit]

The processor implements the following changes:[2][3][4]

  • micro-op (MOP) cache removed (previously 1.5k entries)
  • Decode width: 10
  • Rename / Dispatch width: 10 (increased from 8)
  • Reorder buffer (ROB): 384 entries (increased from 320)
  • Execution ports: 21 (increased from 15)
  • Pipeline length: 10 (increased from 9)
  • Up to 2 MiB of private L2 cache (increased from 1 MiB)
  • DSU-120
    • Up to 14 cores (up from 12 cores)
    • Up to 32 MiB of shared L3 cache (increased from 16 MiB)
  • ARMv9.2

Performance claims:

  • 15% peak performance improvement over the Cortex-X3 in smartphones (3.4GHz, 2MB L2, 8MB L3).[4]
  • 13% IPC uplift over the Cortex-X3, when based on the same process, clock speed, and L3 cache (but 2 MiB L2 vs 1 MiB L2) setup (also known as ISO-process).[4]

Architecture comparison[edit]

uArch Cortex-A78 Cortex-X1 Cortex-X2 Cortex-X3 Cortex-X4 Cortex-X5
Peak clock speed ~3.0 GHz ~3.25 GHz ~3.4 GHz
Decode Width 4 5 6 10[6]
Dispatch 6/cycle 8/cycle 10/cycle
Max In-flight 2x160 2x224 2x288 2x320 2x384
L0 (Mops entries) 1536[7] 3,072[7] 1536 None[6]
L1-I + L1-D 32+32 KiB[8] 64+64 KiB
L2 128–512 KiB 0.256 – 1 MiB 0.5 – 2 MiB
L3 0–8 MiB 0–16 MiB 0–32 MiB
Architecture ARMv8.2 ARMv9 ARMv9.2

Usage[edit]

See also[edit]

References[edit]

  1. ^ Dahad, Nitin (2023-06-02). "Arm Total Compute Solution 2023 targets premium smartphones". Embedded.com. Retrieved 2024-01-17.
  2. ^ a b "Arm Cortex-X4 advances frontiers of CPU performance - Announcements - Arm Community blogs - Arm Community". community.arm.com. 2023-05-29. Retrieved 2023-09-16.
  3. ^ a b "Arm Introduces The Cortex-X4, Its Newest Flagship Performance Core". WikiChip Fuse. 2023-05-28. Retrieved 2023-05-30.
  4. ^ a b c d Bonshor, Gavin. "Arm Unveils 2023 Mobile CPU Core Designs: Cortex-X4, A720, and A520 - the Armv9.2 Family". www.anandtech.com. Retrieved 2023-05-30.
  5. ^ "TCS23: The complete platform for consumer computing - Announcements - Arm Community blogs - Arm Community". community.arm.com. 2023-05-29. Retrieved 2023-09-16.
  6. ^ a b "Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive". Android Authority. 2023-05-29. Retrieved 2023-06-01.
  7. ^ a b Frumusanu, Andrei. "Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence". www.anandtech.com. Retrieved 2023-06-01.
  8. ^ Schor, David (2020-05-26). "Arm Cortex-X1: The First From The Cortex-X Custom Program". WikiChip Fuse. Retrieved 2023-05-30.
  9. ^ "MediaTek says its Snapdragon 8 Gen 3 rival will be a beast (Updated)". Android Authority. 2023-05-29. Retrieved 2023-09-16.
  10. ^ "Qualcomm Snapdragon Tech Summit Live Blog: Compute Spotlight". Android Authority. 2023-05-29. Retrieved 2023-09-16.
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